RISC-V /Debug /Interrupt Trigger (64-bit itrigger)

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Interpret as Interrupt Trigger (64-bit itrigger)

63 6059 5655 5251 4847 4443 4039 3635 3231 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (breakpoint)action0 (u)u0 (s)s0 (m)m0 (nmi)nmi 0 (vu)vu 0 (vs)vs 0 (hit)hit 0 (dmode)dmode 0type

action=breakpoint

Description

This register provides access to the trigger selected by {csr-tselect}. The reset values listed here apply to every underlying trigger.

This register is accessible as {csr-tdata1} when {tdata1-type} is 4.

This trigger can fire when an interrupt trap is taken.

It can be enabled for individual interrupt numbers by setting the bit corresponding to the interrupt number in {csr-tdata2}. The interrupt number is interpreted in the mode that the trap handler executes in. (E.g. virtualized interrupt numbers are not the same in every mode.) In addition the trigger can be enabled for non-maskable interrupts using {itrigger-nmi}.

đź“Ś NOTE

If XLEN is 32, then it is not possible to set a trigger for interrupts with Exception Code larger than 31. A future version of the RISC-V Privileged Spec will likely define interrupt Exception Codes 32 through 47. Some of those numbers are already being used by the RISC-V Advanced Interrupt Architecture.

Hardware may only support a subset of interrupts for this trigger. A debugger must read back {csr-tdata2} after writing it to confirm the requested functionality is actually supported.

When the trigger matches, it fires after the trap occurs, just before the first instruction of the trap handler is executed. If {itrigger-action}=0, the standard CSRs are updated for taking the breakpoint trap, and zero is written to the relevant tval CSR. If the breakpoint trap does not go to a higher privilege mode, this will lose CSR information for the original trap. See nativetrigger for more information about this case.

If {csr-textra32} or {csr-textra64} are implemented for this trigger, it only matches when the conditions set there are satisfied.

Fields

action

The action to take when the trigger fires. The values are explained in tab:action.

0 (breakpoint):

1 (debug mode):

2 (trace on):

3 (trace off):

4 (trace notify):

8 (external0):

9 (external1):

u

When set, enable this trigger for interrupts that are taken from U mode. This bit is hard-wired to 0 if the hart does not support U-mode.

s

When set, enable this trigger for interrupts that are taken from S/HS mode. This bit is hard-wired to 0 if the hart does not support S-mode.

m

When set, enable this trigger for interrupts that are taken from M mode.

nmi

When set, non-maskable interrupts cause this trigger to fire if the trigger is enabled for the current mode.

vu

When set, enable this trigger for interrupts that are taken from VU mode. This bit is hard-wired to 0 if the hart does not support virtualization mode.

vs

When set, enable this trigger for interrupts that are taken from VS mode. This bit is hard-wired to 0 if the hart does not support virtualization mode.

hit

If this bit is implemented, the hardware sets it when this trigger matches. The trigger’s user can set or clear it at any time. It is used to determine which trigger(s) matched. If the bit is not implemented, it is always 0 and writing it has no effect.

dmode
type

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